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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-04-25 19:30:58 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-04-28 15:57:17 +0200 |
| commit | a3d13fbd699e82781b436c88941c6d8d83133400 (patch) | |
| tree | 080b857916ef97435b28b3e746d603c94faf8e59 /src/soc/intel/apollolake/meminit.c | |
| parent | a3cecb2e7116fc80d297db97f2cd7175a4e038fb (diff) | |
| download | coreboot-a3d13fbd699e82781b436c88941c6d8d83133400.tar.xz | |
soc/intel/apollolake: Update default LPDDR4 CA ODT config
Update default ODT config to have correct CA ODT settings as the
current defaults are incorrect for all the current apollolake designs.
All the current designs pull both A and B channels' LPDDR4 modules' ODT
pins to 1.1V. Therefore, the correct impedance setting needs to be
applied.
In order for the settings to take effect one needs to clear the
memory training cache in deployed systems. Trigger this by bumping
the memory setting version for the SoC.
If needed in the future support for allowing the override of this
setting from the mainboard should be straight forward. It's just not
necessary at this time.
BUG=b:37687843
TEST=BAT test, warm, reboot, S3 cycle test
Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19397
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/meminit.c')
| -rw-r--r-- | src/soc/intel/apollolake/meminit.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 9546c19086..0a696746a3 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -73,11 +73,12 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg) cfg->Ch2_Option = 0x3; cfg->Ch3_Option = 0x3; - /* Weak on-die termination. */ - cfg->Ch0_OdtConfig = 0; - cfg->Ch1_OdtConfig = 0; - cfg->Ch2_OdtConfig = 0; - cfg->Ch3_OdtConfig = 0; + /* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled + up to 1.1V. */ + cfg->Ch0_OdtConfig = ODT_A_B_HIGH_HIGH; + cfg->Ch1_OdtConfig = ODT_A_B_HIGH_HIGH; + cfg->Ch2_OdtConfig = ODT_A_B_HIGH_HIGH; + cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH; } void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed) @@ -319,3 +320,9 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) mem_info->dimm_cnt = index; printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } + +uint8_t fsp_memory_soc_version(void) +{ + /* Bump this value when the memory configuration parameters change. */ + return 1; +} |