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authorHannah Williams <hannah.williams@intel.com>2016-05-13 00:47:14 -0700
committerAaron Durbin <adurbin@chromium.org>2016-05-25 19:09:21 +0200
commitd9c84ca7ef0142df99c01832fe8683faec257436 (patch)
treeae68851f5fbe502229692f9d86a07239445d8b0d /src/soc/intel/apollolake/memmap.c
parentba0fc470ddf13af322c79bac291ad475331e09a3 (diff)
downloadcoreboot-d9c84ca7ef0142df99c01832fe8683faec257436.tar.xz
soc/apollolake: SOC specific SMM code
Add SMI handlers that map to SOC specific SMI events Update relocation_handler in mp_ops Change-Id: Idefddaf41cf28240f5f8172b00462a7f893889e7 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14808 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/memmap.c')
-rw-r--r--src/soc/intel/apollolake/memmap.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index bf172cba6e..e57ed53d74 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -20,13 +20,27 @@
#include <device/pci.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
+#include <soc/smm.h>
static uintptr_t smm_region_start(void)
{
return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
}
+static size_t smm_region_size(void)
+{
+ uintptr_t smm_end =
+ ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, BGSM), 1*MiB);
+ return smm_end - smm_region_start();
+}
+
void *cbmem_top(void)
{
return (void *)smm_region_start();
}
+
+void smm_region(void **start, size_t *size)
+{
+ *start = (void *)smm_region_start();
+ *size = smm_region_size();
+}