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| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-21 12:41:20 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-07 20:23:01 +0100 |
| commit | d6c555971b9f9f0c2d49269b0874e3480258531a (patch) | |
| tree | d6dfa1bcbf1f122cac1b3f62f6eb0a86901c45ac /src/soc/intel/apollolake/mmap_boot.c | |
| parent | b5d41cb063a54d2a90e0480ede18d3b9c1ae8474 (diff) | |
| download | coreboot-d6c555971b9f9f0c2d49269b0874e3480258531a.tar.xz | |
soc/intel/apollolake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.
Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/mmap_boot.c')
| -rw-r--r-- | src/soc/intel/apollolake/mmap_boot.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b95b4..7159c24f52 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -22,9 +22,9 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/nvm.h> #include <soc/mmap_boot.h> -#include <soc/spi.h> /* * BIOS region on the flash is mapped right below 4GiB in the address @@ -81,7 +81,7 @@ static void bios_mmap_init(void) * Base and Limit. * Base and Limit fields are in units of 4KiB. */ - uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); + uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> |