diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2016-09-06 18:15:29 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-28 21:56:26 +0200 |
| commit | 9108680c1c17ec539bbba9525b6d9d62e57d296a (patch) | |
| tree | 8e82238a3ea05c54ea3c877928ef78aa94cc11c4 /src/soc/intel/apollolake/pmc.c | |
| parent | f9c41974cd20a392125932c3376c4dfc20455331 (diff) | |
| download | coreboot-9108680c1c17ec539bbba9525b6d9d62e57d296a.tar.xz | |
soc/intel/apollolake: Use fixed resource for SRAM and IPC1
Intel telemetry support will require PMC IPC1 and SRAM devices to be
operated in ACPI mode. Then using fixed resources on BAR0, BAR1
and BAR2 (PMC only) for those two devices will help
the resource assignment in DSDT stage.
BUG=chrome-os-partner:57364
BRANCH=None
TEST=Boot up into Chrome OS successfully and check with dmesg to see
the driver has been loaded successfully without errors.
Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16648
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/pmc.c')
| -rw-r--r-- | src/soc/intel/apollolake/pmc.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 20c9492026..4544e0d60d 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -39,6 +39,11 @@ static void read_resources(device_t dev) struct resource *res; pci_dev_read_resources(dev); + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_BAR0; + res->size = PMC_BAR0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = ACPI_PMIO_BASE; res->size = ACPI_PMIO_SIZE; @@ -58,6 +63,12 @@ static void set_resources(device_t dev) pci_dev_set_resources(dev); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " PMC BAR"); + res = find_resource(dev, PCI_BASE_ADDRESS_4); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_IO; |