soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI Init

CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With 
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table 
entry for this range which caused a page fault. Since this test 
is anyway not exhaustive, we will skip the memory test in FSP.

There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.

FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence 
skipping SPI clock programming in FSP.

CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 13 insertions, 9 deletions

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index bccfc16ba6..cee23b6d6e 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -315,16 +315,20 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
 
 	m_cfg->PrmrrSize = config->PrmrrSize;
 
-	/* FSP performs a PERST# signal deassertion for PCIe ports with
-	 * the GPIO address specified in these UPDs. Over-ride the default
-	 * addresses with 0 to bypass PERST# signal deassertion in FSP.
+	/*
+	 * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init.
+	 * With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page
+	 * table entry for this range which caused a page fault. Since this
+	 * test is anyway not exhaustive, skipping the memory test in FSP.
+	 */
+	m_cfg->SkipMemoryTestUpd = 1;
+
+	/*
+	 * PCIe power sequence can be done from within FSP when provided
+	 * with the GPIOs used for PERST to FSP. Since this is done in
+	 * coreboot, skipping the PCIe power sequence done by FSP.
 	 */
-	m_cfg->RootPort0Perst = 0;
-	m_cfg->RootPort1Perst = 0;
-	m_cfg->RootPort2Perst = 0;
-	m_cfg->RootPort3Perst = 0;
-	m_cfg->RootPort4Perst = 0;
-	m_cfg->RootPort5Perst = 0;
+	m_cfg->SkipPciePowerSequence = 1;
 #endif
 }