soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables

GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.

This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.

BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.

Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 77 insertions, 17 deletions

diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl
index 9f8503341d..9f7304bb57 100644
--- a/src/soc/intel/apollolake/acpi/xhci.asl
+++ b/src/soc/intel/apollolake/acpi/xhci.asl
@@ -34,22 +34,10 @@ Device (XHCI) {
 		/* Root Hub */
 		Name (_ADR, Zero)
 
-		/* USB2 */
-		Device (HS01) { Name (_ADR, 1) }
-		Device (HS02) { Name (_ADR, 2) }
-		Device (HS03) { Name (_ADR, 3) }
-		Device (HS04) { Name (_ADR, 4) }
-		Device (HS05) { Name (_ADR, 5) }
-		Device (HS06) { Name (_ADR, 6) }
-		Device (HS07) { Name (_ADR, 7) }
-		Device (HS08) { Name (_ADR, 8) }
-
-		/* USB3 */
-		Device (SS01) { Name (_ADR, 9) }
-		Device (SS02) { Name (_ADR, 10) }
-		Device (SS03) { Name (_ADR, 11) }
-		Device (SS04) { Name (_ADR, 12) }
-		Device (SS05) { Name (_ADR, 13) }
-		Device (SS06) { Name (_ADR, 14) }
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "xhci_glk_ports.asl"
+#else
+#include "xhci_apl_ports.asl"
+#endif
 	}
 }
diff --git a/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
new file mode 100644
index 0000000000..ebb3e8cd99
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/xhci_apl_ports.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 9) }
+Device (SS02) { Name (_ADR, 10) }
+Device (SS03) { Name (_ADR, 11) }
+Device (SS04) { Name (_ADR, 12) }
+Device (SS05) { Name (_ADR, 13) }
+Device (SS06) { Name (_ADR, 14) }
diff --git a/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
new file mode 100644
index 0000000000..e3b045cc2a
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/xhci_glk_ports.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+Device (HS09) { Name (_ADR, 9) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 10) }
+Device (SS02) { Name (_ADR, 11) }
+Device (SS03) { Name (_ADR, 12) }
+Device (SS04) { Name (_ADR, 13) }
+Device (SS05) { Name (_ADR, 14) }
+Device (SS06) { Name (_ADR, 15) }
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cddfe4436f..de33e8217b 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -121,6 +121,9 @@ const char *soc_acpi_name(const struct device *dev)
 			case 5: return "HS06";
 			case 6: return "HS07";
 			case 7: return "HS08";
+			case 8:
+				if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+					return "HS09";
 			}
 			break;
 		case 3: