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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2018-05-14 23:33:55 -0700
committerAaron Durbin <adurbin@chromium.org>2018-05-22 15:52:20 +0000
commit5af546c5e40835145fee6eff4f43283bea80db91 (patch)
treedd274c0cf0c11ea0d44198841db52084f7cd728b /src/soc/intel/apollolake
parentee3158fd6cf27397384550de613085cc11426009 (diff)
downloadcoreboot-5af546c5e40835145fee6eff4f43283bea80db91.tar.xz
soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI Init
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table entry for this range which caused a page fault. Since this test is anyway not exhaustive, we will skip the memory test in FSP. There is an option to do PCIe power sequence from within FSP if provided with the GPIOs used for PERST to FSP. Since we do this from coreboot, will skip the PCIe power sequence done by FSP. FSP does not know what the clock requirements are for the device on SPI bus, hence it should not modify what coreboot has set up. Hence skipping SPI clock programming in FSP. CQ-DEPEND=CL:*627827 BUG=b:78599939, b:78599576, b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26284 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/chip.c8
-rw-r--r--src/soc/intel/apollolake/romstage.c22
2 files changed, 21 insertions, 9 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 4c8abda7f3..c49f73473e 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -538,6 +538,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
static void glk_fsp_silicon_init_params_cb(
struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
{
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
silconfig->Gmm = 0;
/* On Geminilake, we need to override the default FSP PCIe de-emphasis
@@ -550,6 +551,13 @@ static void glk_fsp_silicon_init_params_cb(
memcpy(silconfig->PcieRpSelectableDeemphasis,
cfg->pcie_rp_deemphasis_enable,
sizeof(silconfig->PcieRpSelectableDeemphasis));
+ /*
+ * FSP does not know what the clock requirements are for the
+ * device on SPI bus, hence it should not modify what coreboot
+ * has set up. Hence skipping in FSP.
+ */
+ silconfig->SkipSpiPCP = 1;
+#endif
}
void __weak mainboard_devtree_update(struct device *dev)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index bccfc16ba6..cee23b6d6e 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -315,16 +315,20 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
m_cfg->PrmrrSize = config->PrmrrSize;
- /* FSP performs a PERST# signal deassertion for PCIe ports with
- * the GPIO address specified in these UPDs. Over-ride the default
- * addresses with 0 to bypass PERST# signal deassertion in FSP.
+ /*
+ * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init.
+ * With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page
+ * table entry for this range which caused a page fault. Since this
+ * test is anyway not exhaustive, skipping the memory test in FSP.
+ */
+ m_cfg->SkipMemoryTestUpd = 1;
+
+ /*
+ * PCIe power sequence can be done from within FSP when provided
+ * with the GPIOs used for PERST to FSP. Since this is done in
+ * coreboot, skipping the PCIe power sequence done by FSP.
*/
- m_cfg->RootPort0Perst = 0;
- m_cfg->RootPort1Perst = 0;
- m_cfg->RootPort2Perst = 0;
- m_cfg->RootPort3Perst = 0;
- m_cfg->RootPort4Perst = 0;
- m_cfg->RootPort5Perst = 0;
+ m_cfg->SkipPciePowerSequence = 1;
#endif
}