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authorNico Huber <nico.huber@secunet.com>2018-11-27 14:15:31 +0100
committerNico Huber <nico.h@gmx.de>2018-12-03 14:47:50 +0000
commit628a3c557d7e4f2ab64cc4497876a70cb106f513 (patch)
treeae032102cc5f3bd1791c6b257be7022f89bee368 /src/soc/intel/apollolake
parent967b1963c8a91028167e5d36e6593f87c91e8531 (diff)
downloadcoreboot-628a3c557d7e4f2ab64cc4497876a70cb106f513.tar.xz
soc/intel/apl: Enable graphics with libgfxinit
Backlight control of internal panels likely won't work as configuration for that seems absent in coreboot. Also, libgfxinit doesn't support any MIPI/DSI connections, yet, and neither Gemini Lake. TEST=Booted work-in-progress port kontron/mal10 with VGA text and linear framebuffer modes. DP display came up. Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/graphics.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 485778833f..37cdda4c47 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -15,19 +15,44 @@
* GNU General Public License for more details.
*/
+#include <stdint.h>
+#include <arch/acpi.h>
#include <arch/acpigen.h>
+#include <bootmode.h>
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/graphics.h>
#include <drivers/intel/gma/opregion.h>
+#include <drivers/intel/gma/libgfxinit.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}
+void graphics_soc_init(struct device *const dev)
+{
+ if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
+ return;
+
+ uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (!acpi_is_wakeup_s3() && display_init_required()) {
+ int lightup_ok;
+ gma_gfxinit(&lightup_ok);
+ gfx_set_init_done(lightup_ok);
+ }
+ } else {
+ /* Initialize PCI device, load/execute BIOS Option ROM */
+ pci_dev_init(dev);
+ }
+}
+
uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{