soc/intel/common: Add SOC specific function to get XHCI USB info

It feels appropriate to define SoC specific XHCI USB info in SoC
specific XHCI source file and an API to get that information instead of
defining it in elog source file. This will help in other situations
where the information is required.

BUG=None
BRANCH=None
TEST=Boot to ChromeOS.

Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 41 insertions, 18 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 4fc16d5891..6fd0822109 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -44,6 +44,7 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += uart.c
 smm-y += elog.c
+smm-y += xhci.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += cpu.c
@@ -67,6 +68,7 @@ ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += xdci.c
 ramstage-y += sd.c
+ramstage-y += xhci.c
 
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c
index c138b346e1..02afb6c5cc 100644
--- a/src/soc/intel/apollolake/elog.c
+++ b/src/soc/intel/apollolake/elog.c
@@ -25,23 +25,6 @@
 #include <soc/smbus.h>
 #include <stdint.h>
 
-#define XHCI_USB2_PORT_STATUS_REG	0x480
-#if CONFIG(SOC_INTEL_GLK)
-#define XHCI_USB3_PORT_STATUS_REG	0x510
-#define XHCI_USB2_PORT_NUM		9
-#else
-#define XHCI_USB3_PORT_STATUS_REG	0x500
-#define XHCI_USB2_PORT_NUM		8
-#endif
-#define XHCI_USB3_PORT_NUM		7
-
-static const struct xhci_usb_info usb_info = {
-	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
-	.num_usb2_ports = XHCI_USB2_PORT_NUM,
-	.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
-	.num_usb3_ports = XHCI_USB3_PORT_NUM,
-};
-
 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {
 	int i;
@@ -74,7 +57,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
 
 	/* XHCI */
 	if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS)
-		pch_xhci_update_wake_event(&usb_info);
+		pch_xhci_update_wake_event(soc_get_xhci_usb_info());
 
 	/* SMBUS Wake */
 	if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS)
diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c
new file mode 100644
index 0000000000..131610756f
--- /dev/null
+++ b/src/soc/intel/apollolake/xhci.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/xhci.h>
+
+#define XHCI_USB2_PORT_STATUS_REG	0x480
+#if CONFIG(SOC_INTEL_GLK)
+#define XHCI_USB3_PORT_STATUS_REG	0x510
+#define XHCI_USB2_PORT_NUM		9
+#else
+#define XHCI_USB3_PORT_STATUS_REG	0x500
+#define XHCI_USB2_PORT_NUM		8
+#endif
+#define XHCI_USB3_PORT_NUM		7
+
+static const struct xhci_usb_info usb_info = {
+	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
+
+const struct xhci_usb_info *soc_get_xhci_usb_info(void)
+{
+	return &usb_info;
+}