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authorShaunak Saha <shaunak.saha@intel.com>2017-12-06 11:22:53 -0800
committerMartin Roth <martinroth@google.com>2017-12-20 16:59:27 +0000
commit41cfd5ba69783c33883d4515ffa15ac279afb831 (patch)
treecd7c1eb29fd5c12341bcd7f9cb94cd1a5073efd5 /src/soc/intel/apollolake
parentac7b506181f94ff2f5974e0205f38d27368c3686 (diff)
downloadcoreboot-41cfd5ba69783c33883d4515ffa15ac279afb831.tar.xz
soc/intel/apollolake: Add SMI and SCI support for ESPI
This patch adds the SMI bits for SMI_EN, SMI_STS and GPE register in pm.h. The southbridge handler for espi smi is also added. In gpe.h we add GPE0A_ESPI_SCI_STS which is bit 20 in GPE register and enables the setting of the ESPI_SCI STS bit to generate a wake event and/or an SCI/SMI. TEST= Boot to OS. Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22758 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/include/soc/gpe.h1
-rw-r--r--src/soc/intel/apollolake/include/soc/pm.h11
-rw-r--r--src/soc/intel/apollolake/smihandler.c3
3 files changed, 14 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h
index eb6e31f47a..53afb03896 100644
--- a/src/soc/intel/apollolake/include/soc/gpe.h
+++ b/src/soc/intel/apollolake/include/soc/gpe.h
@@ -34,6 +34,7 @@
#define GPE0A_SMB_WAK_STS 16
#define GPE0A_SATA_PME_STS 17
#define GPE0A_CNVI_PME_STS 18
+#define GPE0A_ESPI_SCI_STS 20 /* Present in GLK */
/* Group DW0 is reserved in Apollolake */
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 37e4cedc3e..34b9f965ae 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -47,6 +47,7 @@
#define SMI_EN 0x40
+#define SMI_ESPI 28 /* This bit is present in GLK*/
#define SMI_OCP_CSE 27
#define SMI_SPI 26
#define SMI_SPI_SSMI 25
@@ -71,6 +72,11 @@
#define SMI_EOS 1
#define SMI_GBL 0
+#if IS_ENABLED(CONFIG_SOC_ESPI)
+#define ESPI_SMI_EN (1 << SMI_ESPI) /* Valid for GLK with ESPI */
+#else
+#define ESPI_SMI_EN 0
+#endif
#define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */
#define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */
#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */
@@ -97,10 +103,11 @@
* - on TCO events
*/
#define ENABLE_SMI_PARAMS \
- (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)
+ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)
#define SMI_STS 0x44
/* Bits for SMI status */
+#define ESPI_SMI_STS_BIT 28
#define PMC_OCP_SMI_STS 27
#define SPI_SMI_STS 26
#define SPI_SSMI_STS 25
@@ -138,6 +145,7 @@
#define GPE0_C 2
#define GPE0_D 3
#define GPE_STD GPE0_A
+#define ESPI_STS (1 << 20) /* This bit is present in GLK */
#define SATA_PME_STS (1 << 17)
#define SMB_WAK_STS (1 << 16)
#define AVS_PME_STS (1 << 14)
@@ -148,6 +156,7 @@
#define PCIE_GPE_STS (1 << 9)
#define SWGPE_STS (1 << 2)
#define GPE0_EN(x) (0x30 + (x * 4))
+#define ESPI_EN (1 << 20) /* This bit is present in GLK */
#define SATA_PME_EN (1 << 17)
#define SMB_WAK_EN (1 << 16)
#define AVS_PME_EN (1 << 14)
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 22c793051d..37d63a1ba5 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -41,4 +41,7 @@ const smi_handler_t southbridge_smi[32] = {
[GPIO_SMI_STS] = smihandler_southbridge_gpi,
[TCO_SMI_STS] = smihandler_southbridge_tco,
[PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
+#if IS_ENABLED(CONFIG_SOC_ESPI)
+ [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
+#endif
};