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| author | Aaron Durbin <adurbin@chromium.org> | 2016-05-18 11:08:39 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-19 17:11:33 +0200 |
| commit | bea930d7e483e777b3b7ed88632b030a31d1dc4b (patch) | |
| tree | 48cf13ccc2d21e371d94d25e01df152d18607535 /src/soc/intel/apollolake | |
| parent | 0f7885722e4ad1ba76f944f796b535ba66fbf2b3 (diff) | |
| download | coreboot-bea930d7e483e777b3b7ed88632b030a31d1dc4b.tar.xz | |
soc/intel/apollolake: clear up ACPI timer emulation magic constant
The timer emulation works by deriving a frequency based off the
Common Timer Copy with a frequency of 19.2MHz.
The desired frequency = (19.2MHz * multiplier) >> 32;
With that knowledge update the code to let the compiler perform
the necessary math based on target frequency.
Change-Id: I716c7980f0456a7c6072bbaaddd6b7fcd8cd5b37
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14889
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 3 |
2 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cd23f5984b..77d98d98be 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -41,8 +41,13 @@ static void enable_pm_timer(void) { /* ACPI PM timer emulation */ msr_t msr; - /* Multiplier value that somehow 3.579545MHz freq */ - msr.hi = 0x2FBA2E25; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; /* Set PM1 timer IO port and enable*/ msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR); wrmsr(MSR_EMULATE_PM_TMR, msr); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index b731d4f539..78fc0b0df6 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -37,4 +37,7 @@ void apollolake_init_cpus(struct device *dev); #define BASE_CLOCK_MHZ 100 +/* Common Timer Copy (CTC) frequency - 19.2MHz. */ +#define CTC_FREQ 19200000 + #endif /* _SOC_APOLLOLAKE_CPU_H_ */ |