diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-03 20:03:18 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-07 12:09:15 +0200 |
| commit | e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 (patch) | |
| tree | f6a10fc93dddada7e49108a5ad06e71590f2d54c /src/soc/intel/apollolake | |
| parent | e81ce0483db982c741eebdda649111eee22a853b (diff) | |
| download | coreboot-e18e6427d0f3261f9ec361d4418b8fe1dd7cc469.tar.xz | |
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/nvs.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index bdba305081..1548c305eb 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -33,7 +33,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LIDS, 8, // 0x02 - LID State PWRS, 8, // 0x03 - AC Power State DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index GPEI, 64, // 0x11 - 0x18 - GPE Wake Source NHLA, 64, // 0x19 - 0x20 - NHLT Address diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index f9cc49d3ff..e0b223fa48 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -33,7 +33,7 @@ typedef struct global_nvs_t { uint8_t lids; /* 0x02 - LID State */ uint8_t pwrs; /* 0x03 - AC Power State */ uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */ + uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ |