diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-18 15:56:11 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-28 21:47:52 +0000 |
| commit | 360684b41aec795d254dcaac1cefb4acf9e129d3 (patch) | |
| tree | c5bbde89d9734c08e7fea993e0403ee05f570091 /src/soc/intel/apollolake | |
| parent | 5270ce133e068fd35a985b62a22ca64ca2fa9696 (diff) | |
| download | coreboot-360684b41aec795d254dcaac1cefb4acf9e129d3.tar.xz | |
soc/intel/common: add TCC activation functionality
This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index bdd6e8c9d9..d14dd8d3ee 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -73,23 +73,6 @@ static void soc_early_romstage_init(void) P2SB_HPTC_ADDRESS_ENABLE); } -/* Thermal throttle activation offset */ -static void configure_thermal_target(void) -{ - msr_t msr; - const config_t *conf = config_of_soc(); - - if (!conf->tcc_offset) - return; - - msr = rdmsr(MSR_TEMPERATURE_TARGET); - /* Bits 27:24 */ - msr.lo &= ~(TEMPERATURE_TCC_MASK << TEMPERATURE_TCC_SHIFT); - msr.lo |= (conf->tcc_offset & TEMPERATURE_TCC_MASK) - << TEMPERATURE_TCC_SHIFT; - wrmsr(MSR_TEMPERATURE_TARGET, msr); -} - /* * Punit Initialization code. This all isn't documented, but * this is the recipe. @@ -101,7 +84,7 @@ static bool punit_init(void) struct stopwatch sw; /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); /* * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). |