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authorAaron Durbin <adurbin@chromium.org>2017-04-26 15:02:51 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-28 15:58:35 +0200
commit9c86aafe5a18068edb824faf4d2e44f0fefc6411 (patch)
treecad07a6388a956016704d6b798307b06d0933f85 /src/soc/intel/apollolake
parenta3d13fbd699e82781b436c88941c6d8d83133400 (diff)
downloadcoreboot-9c86aafe5a18068edb824faf4d2e44f0fefc6411.tar.xz
soc/intel/apollolake: work around full retrain constraints on warm reset
It's come to attention that apollolake doesn't support a full retrain on warm reset. Therefore force a cold reset when a full retrain is requested in the non-S5 path. BUG=b:37687843 Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19483 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/include/soc/pm.h3
-rw-r--r--src/soc/intel/apollolake/romstage.c18
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index f754541bc2..7db63f6bdc 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -143,6 +143,9 @@
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x1000
#define GEN_PMCON1 0x1020
+#define COLD_BOOT_STS (1 << 27)
+#define COLD_RESET_STS (1 << 26)
+#define WARM_RESET_STS (1 << 25)
#define SRS (1 << 20)
#define RPS (1 << 2)
#define GEN_PMCON2 0x1024
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 0270920c95..c1353c8240 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -31,6 +31,7 @@
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
+#include <reset.h>
#include <soc/cpu.h>
#include <soc/flash_ctrlr.h>
#include <soc/intel/common/mrc_cache.h>
@@ -258,10 +259,27 @@ static void fill_console_params(FSPM_UPD *mupd)
}
}
+static void check_full_retrain(const FSPM_UPD *mupd)
+{
+ struct chipset_power_state *ps;
+
+ if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION)
+ return;
+
+ ps = car_get_var_ptr(&power_state);
+
+ if (ps->gen_pmcon1 & WARM_RESET_STS) {
+ printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
+ hard_reset();
+ }
+}
+
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
struct region_device rdev;
+ check_full_retrain(mupd);
+
fill_console_params(mupd);
mainboard_memory_init_params(mupd);