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authorHannah Williams <hannah.williams@intel.com>2016-04-18 13:47:08 -0700
committerMartin Roth <martinroth@google.com>2016-06-08 22:31:27 +0200
commit0f61da85820c518341240ce0b60ebfec70187fc0 (patch)
treed3205a573289764a5f66b00908ec89c6c6c476d5 /src/soc/intel/apollolake
parentf8daa378614178263b705fbd9e1251bb4b8d148d (diff)
downloadcoreboot-0f61da85820c518341240ce0b60ebfec70187fc0.tar.xz
soc/apollolake: Add SOC specific c-state table
Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/Kconfig1
-rw-r--r--src/soc/intel/apollolake/acpi.c41
-rw-r--r--src/soc/intel/apollolake/chip.c2
3 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 7c21ed2fe0..98ce7d8c3c 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS
select SMM_TSEG
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_SMI
+ select SOC_INTEL_COMMON_ACPI
select SPI_FLASH
select UDELAY_TSC
select TSC_CONSTANT_RATE
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 4d610f85bd..07a5fcbf88 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -22,10 +22,19 @@
#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <soc/acpi.h>
+#include <soc/intel/common/acpi.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <soc/nvs.h>
+#define CSTATE_RES(address_space, width, offset, address) \
+ { \
+ .space_id = address_space, \
+ .bit_width = width, \
+ .bit_offset = offset, \
+ .addrl = address, \
+ }
+
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
@@ -157,3 +166,35 @@ void southbridge_inject_dsdt(device_t device)
acpigen_pop_len();
}
}
+static acpi_cstate_t cstate_map[] = {
+ {
+ /* C1 */
+ .ctype = 1, /* ACPI C1 */
+ .latency = 1,
+ .power = 1000,
+ .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0),
+ },
+ {
+ .ctype = 2, /* ACPI C2 */
+ .latency = 50,
+ .power = 10,
+ .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415),
+ },
+ {
+ .ctype = 3, /* ACPI C3 */
+ .latency = 150,
+ .power = 10,
+ .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419),
+ }
+};
+
+acpi_cstate_t *soc_get_cstate_map(int *entries)
+{
+ *entries = ARRAY_SIZE(cstate_map);
+ return cstate_map;
+}
+
+uint16_t soc_get_acpi_base_address(void)
+{
+ return ACPI_PMIO_BASE;
+}
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 17bceec225..7c8b6387a2 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
@@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = {
.enable_resources = DEVICE_NOOP,
.init = apollolake_init_cpus,
.scan_bus = NULL,
+ .acpi_fill_ssdt_generator = generate_cpu_entries,
};
static void enable_dev(device_t dev)