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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-10 20:28:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-11 12:28:44 +0000 |
| commit | b1c57d1bebb6dd516afa2e85a3f8082a6c77f8ec (patch) | |
| tree | 487860c5c4032829a1b631275195b24bdf24c7b2 /src/soc/intel/baytrail/Kconfig | |
| parent | c9e33573c1b517879ce1199fec98220f0e401076 (diff) | |
| download | coreboot-b1c57d1bebb6dd516afa2e85a3f8082a6c77f8ec.tar.xz | |
soc/intel/baytrail: Use non-evict CAR setup
The CAR setup is almost identical to the cpu/intel/non-evict
CAR setup, with the only difference that L2 cache needs to be
separately enabled. Currently this assumes that it is possible
to use a static Kconfig option to cover all CPU's requiring this.
Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index ade908f3c2..e824ee49a6 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_STAGE select POSTCAR_CONSOLE select CPU_INTEL_COMMON + select CPU_HAS_L2_ENABLE_MSR config VBOOT select VBOOT_STARTS_IN_ROMSTAGE |