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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-31 14:52:20 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-03 06:15:35 +0000
commit0d6ddf8da7632e775dde92c9114ac6ace5ca5f14 (patch)
tree67b37afc2c6bc3cfaa3750a87394c5b056067137 /src/soc/intel/baytrail/Kconfig
parentea2bec2c4b1a986b059147506c99a202d5c8fad3 (diff)
downloadcoreboot-0d6ddf8da7632e775dde92c9114ac6ace5ca5f14.tar.xz
cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/Kconfig')
-rw-r--r--src/soc/intel/baytrail/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index c833c5360f..397e86768c 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select SPI_FLASH
select SSE2
- select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC