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authorMartin Roth <gaumless@gmail.com>2015-06-23 19:59:30 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-02 02:21:33 +0200
commitc407cb97bc121ef28770cdda1d7ee7e2f06157e8 (patch)
tree5241c7bb085600e9233d7bfb2f9b08c4b6fecd0c /src/soc/intel/baytrail/Makefile.inc
parentc528c2e3e9f9e87522ab5b1cd61e67e1dec606ce (diff)
downloadcoreboot-c407cb97bc121ef28770cdda1d7ee7e2f06157e8.tar.xz
Move baytrail & fsp_baytrail to the common IFD interface.
- Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10647 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/Makefile.inc')
-rw-r--r--src/soc/intel/baytrail/Makefile.inc37
1 files changed, 1 insertions, 36 deletions
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 78e2da6556..741752603b 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../southbridge/intel/common/firmware
ramstage-y += memmap.c
romstage-y += memmap.c
@@ -56,40 +57,6 @@ ramstage-y += placeholders.c
CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE:=baytrail_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
- $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
- $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
- printf "\n** WARNING **\n"
- printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
- printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
- printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
- printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
- $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
- printf " DD Adding Intel Firmware Descriptor\n"
- dd if=$(IFD_BIN_PATH) \
- of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
- printf " IFDTOOL me.bin -> coreboot.pre\n"
- $(objutil)/ifdtool/ifdtool \
- -i ME:$(CONFIG_ME_BIN_PATH) \
- $(obj)/coreboot.pre
- mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
# If an MRC file is an ELF file determine the entry address and first loadable
# section offset in the file. Subtract the offset from the entry address to
# determine the final location.
@@ -102,6 +69,4 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS))
mrc.bin-type := mrc
-PHONY += baytrail_add_me
-
endif