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authorAaron Durbin <adurbin@chromium.org>2013-09-27 11:38:36 -0500
committerAaron Durbin <adurbin@google.com>2014-02-05 05:23:08 +0100
commit794bddf97c1c07f5fd12f073f4f5da3f476a1f07 (patch)
tree6a88c9979276c51f732141d23b63578b3188b4e9 /src/soc/intel/baytrail/Makefile.inc
parent818f369da2b0c0df553fd41aad966869653a1d91 (diff)
downloadcoreboot-794bddf97c1c07f5fd12f073f4f5da3f476a1f07.tar.xz
baytrail: start collecting timestamps
This commit always selects COLLECT_TIMESTAMPS and starts tracking TSC values from the early stages of bootblock. The initial timestamp value is saved in mm0 and mm1 while in bootlbock. This approach works because romcc is not configured to use mmx registers for its compilation. Additionally, the romstage api with the mainboard was changed to always pass around a pointer to a romstage_params structure as the timestamps are saved in there until ram is up. BUG=chrome-os-partner:22873 BRANCH=None TEST=Built and booted with added code to print out timestamps at end of ramstage. Everything looks legit. Change-Id: Iba8d5fff1654afa6471088c46a357474ba533236 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170950 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/Makefile.inc')
-rw-r--r--src/soc/intel/baytrail/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index ebcda6b93e..b4474c05a3 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,3 +1,4 @@
+subdirs-y += bootblock
subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic