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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-04 14:51:19 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-27 13:47:11 +0000 |
commit | b48d63359bb4beb63cf2e14edb7b1d833e602ce1 (patch) | |
tree | b0afa3995446bc60aca5d8700cf9d43249a431a9 /src/soc/intel/baytrail/Makefile.inc | |
parent | 4ff63d3a11014fa1a54c82a3023182059c5812f1 (diff) | |
download | coreboot-b48d63359bb4beb63cf2e14edb7b1d833e602ce1.tar.xz |
soc/intel/baytrail: Use sb/intel/common/spi.c
This common implementation is compatible.
Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/baytrail/Makefile.inc')
-rw-r--r-- | src/soc/intel/baytrail/Makefile.inc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d9663462c6..2c49c63454 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -12,12 +12,10 @@ subdirs-y += ../../../cpu/intel/common romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c -romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += iosf.c postcar-y += memmap.c -postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c @@ -43,7 +41,6 @@ ramstage-y += scc.c ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c @@ -52,7 +49,6 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c smm-y += iosf.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += tsc_freq.c # Remove as ramstage gets fleshed out |