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authorDuncan Laurie <dlaurie@chromium.org>2013-11-05 13:02:30 -0800
committerAaron Durbin <adurbin@google.com>2014-05-06 18:39:04 +0200
commit8923be58b87cbf55f5765eca6ce29d7b6827be97 (patch)
treecdccd705ca0ab88a93a69b6dfa49845e008c0deb /src/soc/intel/baytrail/acpi
parent6aa9f1f0eb97e315ab4db8e6da1d13db7ee7858f (diff)
downloadcoreboot-8923be58b87cbf55f5765eca6ce29d7b6827be97.tar.xz
baytrail: Add ACPI CPU entries
- C-state table based on static config MWAIT values are from ref code for non-S0ix config C6 substate 8 is ignored by the kernel as it violates the CPUID but it is left in as the other substate may not work. - P-state table generated with proper ratio and VID values relies on having the package power msr set to magic value as the power-on default is wrong - T-state table uses static table BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175742 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4954 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/acpi')
-rw-r--r--src/soc/intel/baytrail/acpi/globalnvs.asl1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 37a234c485..2f614a9806 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -50,6 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PWRS, 8, // 0x10 - Power State (AC = 1)
PCNT, 8, // 0x11 - Processor count
TPMP, 8, // 0x12 - TPM Present and Enabled
+ TLVL, 8, // 0x13 - Throttle Level
/* Device Config */
Offset (0x20),