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authorAaron Durbin <adurbin@chromium.org>2014-02-05 14:55:26 -0600
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-09-19 21:38:48 +0200
commit4177db52a29b28a023a9ae84ed76c40ed6ce4daf (patch)
treeac380539c9ee151b479af8332a9b14a20b1122d9 /src/soc/intel/baytrail/acpi
parente6b280e24b02552dc43510ed7fadce4a7105e4a2 (diff)
downloadcoreboot-4177db52a29b28a023a9ae84ed76c40ed6ce4daf.tar.xz
baytrail/rambi: spi, charger, and audio updates
baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/acpi')
-rw-r--r--src/soc/intel/baytrail/acpi/dptf/charger.asl43
-rw-r--r--src/soc/intel/baytrail/acpi/dptf/cpu.asl5
-rw-r--r--src/soc/intel/baytrail/acpi/dptf/dptf.asl5
-rw-r--r--src/soc/intel/baytrail/acpi/lpe.asl2
4 files changed, 43 insertions, 12 deletions
diff --git a/src/soc/intel/baytrail/acpi/dptf/charger.asl b/src/soc/intel/baytrail/acpi/dptf/charger.asl
index 7560f139be..7c7f62fb57 100644
--- a/src/soc/intel/baytrail/acpi/dptf/charger.asl
+++ b/src/soc/intel/baytrail/acpi/dptf/charger.asl
@@ -14,23 +14,46 @@ Device (TCHG)
}
}
- Name (PPSS, Package ()
+ /* Return charger performance states defined by mainboard */
+ Method (PPSS)
{
- Package () { 0, 0, 0, 0, 0, 0x880, "mA", 0 }, /* 2.1A */
- Package () { 0, 0, 0, 0, 1, 0x800, "mA", 0 }, /* 2.0A */
- Package () { 0, 0, 0, 0, 2, 0x600, "mA", 0 }, /* 1.5A */
- Package () { 0, 0, 0, 0, 3, 0x400, "mA", 0 }, /* 1.0A */
- Package () { 0, 0, 0, 0, 4, 0x200, "mA", 0 }, /* 0.5A */
- Package () { 0, 0, 0, 0, 5, 0x000, "mA", 0 }, /* 0.0A */
- })
+ Return (\_SB.CHPS)
+ }
+ /* Return maximum charger current limit */
Method (PPPC)
{
+ /* Convert size of PPSS table to index */
+ Store (SizeOf (\_SB.CHPS), Local0)
+ Decrement (Local0)
+
+ /* Check if charging is disabled (AC removed) */
+ If (LEqual (\PWRS, Zero)) {
+ /* Return last power state */
+ Return (Local0)
+ } Else {
+ /* Return highest power state */
+ Return (0)
+ }
+
Return (0)
}
- Method (SPPC, 1, Serialized)
+ /* Set charger current limit */
+ Method (SPPC, 1)
+ {
+ /* Retrieve Control (index 4) for specified PPSS level */
+ Store (DeRefOf (Index (DeRefOf (Index
+ (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+ /* Pass Control value to EC to limit charging */
+ \_SB.PCI0.LPCB.EC0.CHGS (Local0)
+ }
+
+ /* Initialize charger participant */
+ Method (INIT)
{
- /* TODO: Tell EC to limit battery charging */
+ /* Disable charge limit */
+ \_SB.PCI0.LPCB.EC0.CHGD ()
}
}
diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl
index 93d434b8b4..89f9b8b02a 100644
--- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl
+++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl
@@ -115,7 +115,10 @@ Device (TCPU)
Method (_PDL)
{
- If (CondRefOf (\_PR.CPU0._PSS)) {
+ /* Check for mainboard specific _PDL override */
+ If (CondRefOf (\_SB.MPDL)) {
+ Return (\_SB.MPDL)
+ } ElseIf (CondRefOf (\_PR.CPU0._PSS)) {
Store (SizeOf (\_PR.CPU0._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
index a54478cd05..9ebfb8c9ce 100644
--- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl
+++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
@@ -36,6 +36,11 @@ Device (DPTF)
If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) {
/* Initialize Thermal Devices */
^TINI ()
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Initialize Charger Device */
+ ^TCHG.INIT ()
+#endif
}
Return (Arg3)
diff --git a/src/soc/intel/baytrail/acpi/lpe.asl b/src/soc/intel/baytrail/acpi/lpe.asl
index 71a2746533..dfa555c834 100644
--- a/src/soc/intel/baytrail/acpi/lpe.asl
+++ b/src/soc/intel/baytrail/acpi/lpe.asl
@@ -74,7 +74,7 @@ Device (LPEA)
/* Append any Mainboard defined GPIOs */
If (CondRefOf (^GBUF, Local0)) {
- ConcatenateResTemplate (^RBUF, Local0, Local1)
+ ConcatenateResTemplate (^RBUF, ^GBUF, Local1)
Return (Local1)
}