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authorAaron Durbin <adurbin@chromium.org>2013-09-07 00:41:48 -0500
committerAaron Durbin <adurbin@google.com>2014-01-31 16:36:59 +0100
commit9a7d7bcea5c3a7bbf956c0909af121a870af515e (patch)
tree4a60a46dbcc901f93ba3a4730dc1875bab61a708 /src/soc/intel/baytrail/bootblock
parentba6b07e88884c62b4075b4e7156fc205e7f7971e (diff)
downloadcoreboot-9a7d7bcea5c3a7bbf956c0909af121a870af515e.tar.xz
baytrail: add initial support
The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/bootblock')
-rw-r--r--src/soc/intel/baytrail/bootblock/bootblock.c39
1 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c
new file mode 100644
index 0000000000..66120d9125
--- /dev/null
+++ b/src/soc/intel/baytrail/bootblock/bootblock.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/iosf.h>
+
+static void bootblock_cpu_init(void)
+{
+ uint32_t reg;
+
+ /* Set up the MMCONF range. The register lives in the BUNIT. The
+ * IO variant of the config access needs to be used initially to
+ * properly configure as the IOSF access registers live in PCI
+ * config space. */
+ reg = 0;
+ /* Clear the extended register. */
+ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
+ reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
+ pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
+ reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
+ IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
+ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
+}