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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-12-02 10:14:47 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-08 07:05:29 +0200 |
| commit | 22f1dcdfc4f7e990e65a72ff9f34d74754208df6 (patch) | |
| tree | 33dabed248acf9d1fdc4f8bb5fcbececcb24ff23 /src/soc/intel/baytrail/chip.h | |
| parent | 5b33dc1ec922ca0025472d87a51bf1b7844b03e6 (diff) | |
| download | coreboot-22f1dcdfc4f7e990e65a72ff9f34d74754208df6.tar.xz | |
baytrail: Update to microcode 31E and fix C-state table
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now
Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4984
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/chip.h')
0 files changed, 0 insertions, 0 deletions