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author | Duncan Laurie <dlaurie@chromium.org> | 2015-01-20 07:53:27 -0800 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:17:53 +0200 |
commit | ff0f460e764e24d4f7bae7e9dce8967f9cd3e36c (patch) | |
tree | b46032b2780d0b1e7588e7bdba031ad58f55e82d /src/soc/intel/baytrail/chip.h | |
parent | ba081ef50dd6cd62de1165e8315aca9b3a40c337 (diff) | |
download | coreboot-ff0f460e764e24d4f7bae7e9dce8967f9cd3e36c.tar.xz |
broadwell: Add configuration for tuning VR for C-state operations
Add some configuration options that allow tuning the VR for C-state
settings that may be able to reduce noise.
- Add option to enable slow VR ramp rate for C-state exit
- Add variable to configure the minimum C6/C7 voltage
BUG=chrome-os-partner:34771
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: I01445d62fbfcf200b787b924d8d72685819a4715
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: ed8f355e60292c82791817ae31bff58ac2390a72
Original-Change-Id: I8af75b69c8b55d3e210170ee96f8e22c2fd76374
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/chip.h')
0 files changed, 0 insertions, 0 deletions