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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-11-05 12:59:50 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-06 17:20:07 +0200 |
| commit | 05a3393a2c089d0c7ad7443e2298dacd129fadb3 (patch) | |
| tree | 069c9e0c6ce4986f7a5aff7c7309ab912e0ca5a5 /src/soc/intel/baytrail/cpu.c | |
| parent | fd461e396b482cd5d0cd81cb11c4973f4ebfa94c (diff) | |
| download | coreboot-05a3393a2c089d0c7ad7443e2298dacd129fadb3.tar.xz | |
baytrail: Enable Turbo/Burst and set some magic MSRs
As far as I can tell turbo enabling behaves like
it did on haswell so use the standard code.
There are also some magic values to set in some magic
MSRs related to turbo and package power so they report
correctly.
The L2 cache shrink is enabled and a threshold is set
that makes both dual and quad core happy.
C1E is disabled to match the reference code.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4952
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/cpu.c')
| -rw-r--r-- | src/soc/intel/baytrail/cpu.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index c55053103c..e3bdc422e0 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -21,13 +21,16 @@ #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <reg_script.h> +#include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/ramstage.h> #include <baytrail/smm.h> @@ -48,6 +51,26 @@ static int adjust_apic_id(int index, int apic_id) return 2 * index; } +/* Package level MSRs */ +const struct reg_script package_msr_script[] = { + /* Set Package TDP to ~7W */ + REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), + REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), + REG_SCRIPT_END +}; + +/* Core level MSRs */ +const struct reg_script core_msr_script[] = { + /* Dynamic L2 shrink enable and threshold */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_MSR_OR(MSR_POWER_MISC, 0x44), + REG_SCRIPT_END +}; + void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -66,6 +89,12 @@ void baytrail_init_cpus(device_t dev) mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = pattrs->microcode_patch; + /* Set package MSRs */ + reg_script_run(package_msr_script); + + /* Enable Turbo/Burst Mode */ + enable_turbo(); + if (mp_init(cpu_bus, &mp_params)) { printk(BIOS_ERR, "MP initialization failure.\n"); } @@ -74,6 +103,12 @@ void baytrail_init_cpus(device_t dev) static void baytrail_core_init(device_t cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); + + /* Set core MSRs */ + reg_script_run(core_msr_script); + + /* Set this core to max frequency ratio */ + set_max_freq(); } static struct device_operations cpu_dev_ops = { |