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author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-11 22:44:41 -0500 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-14 11:16:41 +0000 |
commit | be33a674bb5d7081d77077d9d486bcc45b2624cd (patch) | |
tree | 3a4a5699770cda85e7a99d8614c63f63517532f3 /src/soc/intel/baytrail/gfx.c | |
parent | 681ef51d731617a0a4d5b604d561acdecb9c9cfa (diff) | |
download | coreboot-be33a674bb5d7081d77077d9d486bcc45b2624cd.tar.xz |
soc/intel/baytrail: add support for Intel GMA OpRegion
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to generate ACPI OpRegion, save the
table address in ASLB, and restore table address upon S3 resume.
Implementation largely based on existing Broadwell code.
Test: boot Windows 10 on google/squawks with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: Iab15e1de2bb7d8fbec2e8705a621cfca0f255d4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/baytrail/gfx.c')
-rw-r--r-- | src/soc/intel/baytrail/gfx.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 57e13291ae..45bcd7ba7d 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -19,13 +19,16 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/opregion.h> #include <reg_script.h> #include <stdlib.h> #include <soc/gfx.h> #include <soc/iosf.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <cbmem.h> #include "chip.h" @@ -362,6 +365,19 @@ static void gfx_panel_setup(device_t dev) } } +uintptr_t gma_get_gnvs_aslb(const void *gnvs) +{ + const global_nvs_t *gnvs_ptr = gnvs; + return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); +} + +void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) +{ + global_nvs_t *gnvs_ptr = gnvs; + if (gnvs_ptr) + gnvs_ptr->aslb = aslb; +} + static void gfx_init(device_t dev) { /* Pre VBIOS Init */ @@ -377,6 +393,35 @@ static void gfx_init(device_t dev) /* Post VBIOS Init */ gfx_post_vbios_init(dev); + + /* Restore opregion on S3 resume */ + intel_gma_restore_opregion(); +} + +static unsigned long +gma_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + igd_opregion_t *opregion = (igd_opregion_t *)current; + global_nvs_t *gnvs; + + if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) + return current; + + current += sizeof(igd_opregion_t); + + /* GNVS has been already set up */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs) { + /* IGD OpRegion Base Address */ + gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + } else { + printk(BIOS_ERR, "Error: GNVS table not found.\n"); + } + + current = acpi_align_current(current); + return current; } static struct device_operations gfx_device_ops = { @@ -385,6 +430,7 @@ static struct device_operations gfx_device_ops = { .enable_resources = pci_dev_enable_resources, .init = gfx_init, .ops_pci = &soc_pci_ops, + .write_acpi_tables = gma_write_acpi_tables, }; static const struct pci_driver gfx_driver __pci_driver = { |