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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-12-09 14:38:57 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-09 05:42:40 +0200 |
| commit | b40e444aee50c4b9768b596f0d7cf726f8d2c10f (patch) | |
| tree | ce52eb52b0234f9755fea0bc39d090547d677975 /src/soc/intel/baytrail/gfx.c | |
| parent | 7b35706cf351675fc7b120a1d1d68baa9e2c717c (diff) | |
| download | coreboot-b40e444aee50c4b9768b596f0d7cf726f8d2c10f.tar.xz | |
baytrail: Enable panel and set timings
These need to be set before the kernel will work without
running the VBIOS option rom.
Also necessary is setting the PP_CONTROL register with
the EDP_FORCE_VDD bit.
BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up
Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5000
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/gfx.c')
| -rw-r--r-- | src/soc/intel/baytrail/gfx.c | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 28b73d5b0b..d2a8ba5d2e 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -30,6 +30,8 @@ #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include "chip.h" + #define GFX_TIMEOUT 100000 /* 100ms */ /* @@ -288,6 +290,77 @@ static void gfx_post_vbios_init(device_t dev) gfx_run_script(dev, gfx_post_vbios_script); } +static void gfx_panel_setup(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + struct reg_script gfx_pipea_init[] = { + REG_SCRIPT_SET_DEV(dev), + /* CONTROL */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + /* HOTPLUG */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL), + 0x1 | (config->gpu_pipea_hotplug << 2)), + /* POWER ON */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), + (config->gpu_pipea_port_select << 30 | + config->gpu_pipea_power_on_delay << 16 | + config->gpu_pipea_light_on_delay)), + /* POWER OFF */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), + (config->gpu_pipea_power_off_delay << 16 | + config->gpu_pipea_light_off_delay)), + /* DIVISOR */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipea_power_cycle_delay), + /* BACKLIGHT */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL), + (config->gpu_pipea_backlight_pwm << 16) | + (config->gpu_pipea_backlight_pwm >> 1)), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2), + BACKLIGHT_ENABLE), + REG_SCRIPT_END + }; + struct reg_script gfx_pipeb_init[] = { + REG_SCRIPT_SET_DEV(dev), + /* CONTROL */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + /* HOTPLUG */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL), + 0x1 | (config->gpu_pipeb_hotplug << 2)), + /* POWER ON */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), + (config->gpu_pipeb_port_select << 30 | + config->gpu_pipeb_power_on_delay << 16 | + config->gpu_pipeb_light_on_delay)), + /* POWER OFF */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), + (config->gpu_pipeb_power_off_delay << 16 | + config->gpu_pipeb_light_off_delay)), + /* DIVISOR */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipeb_power_cycle_delay), + /* BACKLIGHT */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL), + (config->gpu_pipeb_backlight_pwm << 16) | + (config->gpu_pipeb_backlight_pwm >> 1)), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2), + BACKLIGHT_ENABLE), + REG_SCRIPT_END + }; + + if (config->gpu_pipea_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); + reg_script_run(gfx_pipea_init); + } + + if (config->gpu_pipeb_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); + reg_script_run(gfx_pipeb_init); + } +} + static void gfx_init(device_t dev) { /* Pre VBIOS Init */ @@ -296,6 +369,8 @@ static void gfx_init(device_t dev) /* Power Management Init */ gfx_pm_init(dev); + gfx_panel_setup(dev); + /* Run VBIOS */ pci_dev_init(dev); |