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authorShawn Nematbakhsh <shawnn@chromium.org>2013-10-08 11:31:21 -0700
committerAaron Durbin <adurbin@google.com>2014-02-11 22:19:32 +0100
commit3b036f71075cb5860d41a8fb83cd885d2044181c (patch)
tree8b077657f60fe1fec79de06b95237f52f38f2d37 /src/soc/intel/baytrail/gpio.c
parentbb3ee8371160e7ffc4d2f4e6de870b7fa3e01d70 (diff)
downloadcoreboot-3b036f71075cb5860d41a8fb83cd885d2044181c.tar.xz
baytrail: Add functions to peek at GPIO input values
- Add functions to peek at GPIO input pad values (need to be used from romstage for board ram_id GPIOs) - Modify UART GPIOs to use existing fn-assignment function TEST=Manual. Add debug print and verify that GPIO functions return input values. Also, verify UART still functions in romstage. BUG=chrome-os-partner:22865 Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4870 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/gpio.c')
-rw-r--r--src/soc/intel/baytrail/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 8118aeb755..9ae79c9d4d 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -44,7 +44,7 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
{ 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
- 26, 51, 56, 54, 49, 55, 48, 47, 50, 58,
+ 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
52, 53, 59, 40 };
/* GPIO bank descriptions */