diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-11 12:09:28 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:39:22 +0200 |
| commit | 59a4cd55782f1148d37f0c2408657ba93deefc86 (patch) | |
| tree | ec8afec917b945d042b753a4043219a49798bb0c /src/soc/intel/baytrail/gpio.c | |
| parent | 997d25219b67704ba497a3d67f392a8a743a1782 (diff) | |
| download | coreboot-59a4cd55782f1148d37f0c2408657ba93deefc86.tar.xz | |
baytrail: add support for routing gpio pins to smi/sci
In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.
The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
and toggling PCH_WAKE_L on the EC console.
Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4957
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/gpio.c')
| -rw-r--r-- | src/soc/intel/baytrail/gpio.c | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 2916c999b6..824ed6560b 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <baytrail/gpio.h> #include <device/pci.h> #include <console/console.h> +#include <baytrail/gpio.h> +#include <baytrail/pmc.h> +#include <baytrail/smm.h> /* GPIO-to-Pad LUTs */ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = @@ -154,12 +156,36 @@ static void setup_gpios(const struct soc_gpio_map *gpios, } } +static void setup_gpio_route(const struct soc_gpio_map *sus, + const struct soc_gpio_map *core) +{ + uint32_t route_reg = 0; + int i; + + for (i = 0; i < 8; i++) { + /* SMI takes precedence and wake_en implies SCI. */ + if (sus[i].smi) { + route_reg |= ROUTE_SMI << (2 * i); + } else if (sus[i].wake_en) { + route_reg |= ROUTE_SCI << (2 * i); + } + + if (core[i].smi) { + route_reg |= ROUTE_SMI << (2 * (i + 8)); + } else if (core[i].wake_en) { + route_reg |= ROUTE_SCI << (2 * (i + 8)); + } + } + southcluster_smm_save_gpio_route(route_reg); +} + void setup_soc_gpios(struct soc_gpio_config *config) { if (config) { setup_gpios(config->ncore, &gpncore_bank); setup_gpios(config->score, &gpscore_bank); setup_gpios(config->ssus, &gpssus_bank); + setup_gpio_route(config->ssus, config->score); } } |