diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2013-11-08 16:43:34 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:40:04 +0200 |
| commit | fb494d68ff92d036adf10fb7eacf97ed9f1a4391 (patch) | |
| tree | 8488428eca8ba4f25db2f2c3b3830bc7e955ee15 /src/soc/intel/baytrail/gpio.c | |
| parent | 7e9634ffc0d48e471cb4c2ff521c6f4361207303 (diff) | |
| download | coreboot-fb494d68ff92d036adf10fb7eacf97ed9f1a4391.tar.xz | |
baytrail: gpio: Add support for direct / dedicated IRQs
Add support for DirectIRQ / dedicated IRQs. This consists of up to 16
IRQs for both SCORE and SSUS banks.
BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.
Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c
Reviewed-on: https://chromium-review.googlesource.com/176165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4962
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/gpio.c')
| -rw-r--r-- | src/soc/intel/baytrail/gpio.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 824ed6560b..8cc7cc0c0c 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -179,6 +179,25 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, southcluster_smm_save_gpio_route(route_reg); } +static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], + const struct gpio_bank *bank) +{ + u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET; + u32 val; + int i; + + /* Write all four DIRQ registers */ + for (i=0; i<4; ++i) { + val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | + dirq[i * 4 + 1] << 8 | dirq[i * 4]; + write32(reg + i * 4, val); +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", + reg + i * 4, val); +#endif + } +} + void setup_soc_gpios(struct soc_gpio_config *config) { if (config) { @@ -186,7 +205,13 @@ void setup_soc_gpios(struct soc_gpio_config *config) setup_gpios(config->score, &gpscore_bank); setup_gpios(config->ssus, &gpssus_bank); setup_gpio_route(config->ssus, config->score); + + if (config->core_dirq) + setup_dirqs(*config->core_dirq, &gpscore_bank); + if (config->sus_dirq) + setup_dirqs(*config->sus_dirq, &gpssus_bank); } + } struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) |