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authorAaron Durbin <adurbin@chromium.org>2016-07-13 23:20:07 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:31:56 +0200
commitf5cfaa39342bed7dbf3abe19486089c4cf8a4561 (patch)
tree9eda5fa75385b45dd5f618a024b22ef48da4e63f /src/soc/intel/baytrail/include
parent56db47fe204482093b23034030f7a7060c5c977b (diff)
downloadcoreboot-f5cfaa39342bed7dbf3abe19486089c4cf8a4561.tar.xz
soc/intel/baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15669 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/include')
-rw-r--r--src/soc/intel/baytrail/include/soc/pmc.h9
1 files changed, 1 insertions, 8 deletions
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index d61b7005cc..c8d6a67a81 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -16,6 +16,7 @@
#ifndef _BAYTRAIL_PMC_H_
#define _BAYTRAIL_PMC_H_
+#include <arch/acpi.h>
#define IOCOM1 0x3f8
@@ -147,14 +148,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP_SHIFT 10
-#define SLP_TYP (7 << SLP_TYP_SHIFT)
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)