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| author | Ben Gardner <gardner.ben@gmail.com> | 2015-11-19 16:12:21 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-21 03:41:34 +0100 |
| commit | 2d3d1b7eee52bca47ab08730be99336c021d0f7c (patch) | |
| tree | e1578c53643da8391e0e02f06f9d5490a5eb66d7 /src/soc/intel/baytrail/include | |
| parent | 42b6265035a58bae254b701ec2a8fcc7d1ebb4a2 (diff) | |
| download | coreboot-2d3d1b7eee52bca47ab08730be99336c021d0f7c.tar.xz | |
baytrail: add C0 and D0 stepping decode
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11.
Add that so the debug log shows 'D0' instead of '??'.
Also, add the C0 stepping decode to fsp_baytrail.
Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/baytrail/include')
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/lpc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/include/soc/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h index 97de16fc87..b3fa6de98d 100644 --- a/src/soc/intel/baytrail/include/soc/lpc.h +++ b/src/soc/intel/baytrail/include/soc/lpc.h @@ -33,6 +33,8 @@ #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 #define RID_C_STEPPING_START 0xe +#define RID_D_STEPPING_START 0x11 + enum baytrail_stepping { STEP_A0, STEP_A1, @@ -41,6 +43,7 @@ enum baytrail_stepping { STEP_B2, STEP_B3, STEP_C0, + STEP_D0, }; /* Registers behind the RCBA_BASE_ADDRESS bar. */ |