baytrail: add initial support

The initial Bay Trail code is intended to support
the mobile and desktop version of Bay Trail. This support
can train memory and execute through ramstage. However,
the resource allocation is not curently handled correctly.
The MRC cache parameters are successfully saved and reused
after the initial cold boot.

BUG=chrome-os-partner:22292
BRANCH=None
TEST=Built and booted on a reference board through ramstage.

Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168387
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4847
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

1 files changed, 61 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
new file mode 100644
index 0000000000..6d4cba9bb6
--- /dev/null
+++ b/src/soc/intel/baytrail/iosf.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/iosf.h>
+
+#if !defined(__PRE_RAM__)
+#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
+
+static inline void write_iosf_reg(int reg, uint32_t value)
+{
+	write32(IOSF_PCI_BASE + reg, value);
+}
+static inline uint32_t read_iosf_reg(int reg)
+{
+	return read32(IOSF_PCI_BASE + reg);
+}
+#else
+static inline void write_iosf_reg(int reg, uint32_t value)
+{
+	pci_write_config32(IOSF_PCI_DEV, reg, value);
+}
+static inline uint32_t read_iosf_reg(int reg)
+{
+	return pci_read_config32(IOSF_PCI_DEV, reg);
+}
+#endif
+
+uint32_t iosf_bunit_read(int reg)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) |
+	              IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;
+
+	write_iosf_reg(MCR_REG, cr);
+	return read_iosf_reg(MDR_REG);
+}
+
+void iosf_bunit_write(int reg, uint32_t val)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) |
+	              IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;
+
+	write_iosf_reg(MCR_REG, cr);
+	write_iosf_reg(MDR_REG, val);
+}