diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-10-31 08:20:48 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-27 06:33:50 +0100 |
| commit | 0854c84735175ea29c8df74dd9d7124a0c1a415b (patch) | |
| tree | 276645db96738798fe4ee95a63f9fa9c3334b38d /src/soc/intel/baytrail/iosf.c | |
| parent | 5d53554d41873993a17b75acaf2c5a2581ee90dd (diff) | |
| download | coreboot-0854c84735175ea29c8df74dd9d7124a0c1a415b.tar.xz | |
baytrail: Add IOSF functions for USBPHY and USHPHY
These are needed for USB2 and USB3 PHY init sequences.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi
Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4916
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/iosf.c')
| -rw-r--r-- | src/soc/intel/baytrail/iosf.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index b050eba5e4..7d420cc627 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -121,3 +121,47 @@ void iosf_punit_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_usbphy_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | + IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | + IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} + +uint32_t iosf_ushphy_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | + IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_ushphy_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | + IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} |