diff options
author | Aaron Durbin <adurbin@chromium.org> | 2013-12-10 17:12:44 -0800 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-10 06:31:29 +0200 |
commit | 616f394d3656760deb1e048c0dde4fe3aaa6607f (patch) | |
tree | 89678eaa7536c943f7b2d21a6bd2d9c26c5a9b73 /src/soc/intel/baytrail/lpss.c | |
parent | cffe795dc1516607421bf770eab45076087fc461 (diff) | |
download | coreboot-616f394d3656760deb1e048c0dde4fe3aaa6607f.tar.xz |
baytrail: utilize reg_script_run_on_dev()
The inclusion of reg_script_run_on_dev() allows
for removing some of the chained reg_scripts just
to set up the device context. Use the new reg_script
function in those cases.
BUG=None
BRANCH=None
TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
console output.
Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
Signed-off-by: Aaron Durbin <adurbin@chromium.og>
Reviewed-on: https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5009
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/lpss.c')
-rw-r--r-- | src/soc/intel/baytrail/lpss.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index e009c7d010..a543fd858c 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -36,7 +36,6 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -68,20 +67,19 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.lpss_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), REG_SCRIPT_END, }; - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) @@ -128,8 +126,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) static void i2c_disable_resets(device_t dev) { /* Release the I2C devices from reset. */ - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script ops[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), REG_SCRIPT_END, }; @@ -146,7 +143,7 @@ static void i2c_disable_resets(device_t dev) CASE_I2C(I2C6): CASE_I2C(I2C7): printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); break; default: return; |