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authorJulius Werner <jwerner@chromium.org>2014-10-07 16:42:17 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-07 18:23:21 +0200
commit18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754 (patch)
tree875739d499ccc1fa84b03507f8bee699fb86eb95 /src/soc/intel/baytrail/lpss.c
parent26de1126363218cd19524050d80acc8ed1ce3e53 (diff)
downloadcoreboot-18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754.tar.xz
baytrail: Change all SoC headers to <soc/headername.h> system
This patch aligns baytrail to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Rambi. Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083 Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/lpss.c')
-rw-r--r--src/soc/intel/baytrail/lpss.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index 3ee648a55c..caa945cc31 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -26,10 +26,10 @@
#include <device/pci_ids.h>
#include <reg_script.h>
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
#include "chip.h"