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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-07-24 20:50:12 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-10 21:10:59 +0200 |
| commit | 09115a92f6ac6123a6f1ed435c05fe60dc01d58c (patch) | |
| tree | 9c6b16087c872cb140c5b447c33ebae3a78e2e23 /src/soc/intel/baytrail/memmap.c | |
| parent | a46ee4d34d6b7ce7d47882779c7fb36270ccbda1 (diff) | |
| download | coreboot-09115a92f6ac6123a6f1ed435c05fe60dc01d58c.tar.xz | |
soc/apollolake: add GPIO SMI support
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS
register. This patch also sets the SMI_EN bit in enable register for
each community based on GPIOROUTSMI bit in gpio pad. When SMI on a
gpio happens status needs to be gathered on gpio number which is done
by reading the GPI_SMI_STS and GPI_SMI_EN registers.
BUG=chrome-os-partner:54977
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15833
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/memmap.c')
0 files changed, 0 insertions, 0 deletions