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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-25 21:07:59 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:09:42 +0200 |
| commit | 4a83f1cf24b793db40606febb8e27cee90452590 (patch) | |
| tree | 74943b190d2aa7c97da72d59f816157d4bc947e9 /src/soc/intel/baytrail/pcie.c | |
| parent | 3c80408fc8aa7b4099493acd7420f8d62ce65a48 (diff) | |
| download | coreboot-4a83f1cf24b793db40606febb8e27cee90452590.tar.xz | |
src/soc: Add required space before opening parenthesis '('
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/pcie.c')
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 5c6275d434..b5d18a0aca 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -197,7 +197,7 @@ static void check_device_present(device_t dev) reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } - } else if(!dev->enabled) { + } else if (!dev->enabled) { /* Port is disabled, but device present. Disable link. */ pci_write_config32(dev, LCTL, pci_read_config32(dev, LCTL) | LD); |