diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-12-10 17:12:44 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-10 06:31:29 +0200 |
| commit | 616f394d3656760deb1e048c0dde4fe3aaa6607f (patch) | |
| tree | 89678eaa7536c943f7b2d21a6bd2d9c26c5a9b73 /src/soc/intel/baytrail/pcie.c | |
| parent | cffe795dc1516607421bf770eab45076087fc461 (diff) | |
| download | coreboot-616f394d3656760deb1e048c0dde4fe3aaa6607f.tar.xz | |
baytrail: utilize reg_script_run_on_dev()
The inclusion of reg_script_run_on_dev() allows
for removing some of the chained reg_scripts just
to set up the device context. Use the new reg_script
function in those cases.
BUG=None
BRANCH=None
TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
console output.
Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
Signed-off-by: Aaron Durbin <adurbin@chromium.og>
Reviewed-on: https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5009
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/pcie.c')
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index f68304df06..ce76d6d88f 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -90,7 +90,6 @@ static const struct reg_script init_static_after_exit_latency[] = { static void byt_pcie_init(device_t dev) { struct reg_script init_script[] = { - REG_SCRIPT_SET_DEV(dev), REG_SCRIPT_NEXT(init_static_before_exit_latency), /* Exit latency configuration based on * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ @@ -108,7 +107,7 @@ static void byt_pcie_init(device_t dev) REG_SCRIPT_END, }; - reg_script_run(init_script); + reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -157,19 +156,13 @@ static void check_port_enabled(device_t dev) static void check_device_present(device_t dev) { - struct reg_script no_dev[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(no_dev_behind_port), - REG_SCRIPT_END, - }; - /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); - reg_script_run(no_dev); + reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } else if(!dev->enabled) { /* Port is disabled, but device present. Disable link. */ |