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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-14 05:41:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 06:55:59 +0000 |
| commit | faf20d30a6e451d45e29613e3f4603dc72771843 (patch) | |
| tree | d1c3df6e87473d66633fb3a4a8cec736fdda2cd7 /src/soc/intel/baytrail/pcie.c | |
| parent | f091f4daf7e76cff3cdf9b7a19bb77281fb6af9d (diff) | |
| download | coreboot-faf20d30a6e451d45e29613e3f4603dc72771843.tar.xz | |
soc/intel: Rename some SMM support functions
Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.
Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/pcie.c')
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index b2b2d3c3b4..6dc0346b23 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -215,7 +215,7 @@ static void byt_pcie_enable(struct device *dev) strpfusecfg = pci_read_config32(dev, STRPFUSECFG); if (config->pcie_wake_enable) - southcluster_smm_save_param( + smm_southcluster_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } |