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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 17:25:38 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-25 10:17:40 +0000
commite80d17f602e841e826e0892e4e44c9e1a9810cc0 (patch)
tree43bde154b250343252fc6655492250b875681d93 /src/soc/intel/baytrail/pmutil.c
parente4109ff54ff3268fe65739e8efe79b57e67d2e3c (diff)
downloadcoreboot-e80d17f602e841e826e0892e4e44c9e1a9810cc0.tar.xz
soc/intel/baytrail: Retype some pointers
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/pmutil.c')
-rw-r--r--src/soc/intel/baytrail/pmutil.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 92e58a018b..319a35fe20 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -338,12 +338,12 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
- gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
+ prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
- write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
+ write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
+ write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}
int rtc_failure(void)