summaryrefslogtreecommitdiff
path: root/src/soc/intel/baytrail/reset.c
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2017-12-21 13:40:07 -0800
committerAaron Durbin <adurbin@chromium.org>2018-01-16 19:40:00 +0000
commit9b50a57e4343ce77b8ae1aaca5a3866599056456 (patch)
treecaecc08a336a560cc1acbc1f3651abde31831b5e /src/soc/intel/baytrail/reset.c
parent7210ec0dcaca84957a5ebe9ea6e222d55a1431bb (diff)
downloadcoreboot-9b50a57e4343ce77b8ae1aaca5a3866599056456.tar.xz
soc/intel/cannonlake: Program DMI PCR settings
According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/reset.c')
0 files changed, 0 insertions, 0 deletions