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author | Nico Huber <nico.h@gmx.de> | 2018-10-06 18:20:47 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:34:56 +0000 |
commit | 73c11194b0ea6a4fb93456fdff36cbd91838d4ec (patch) | |
tree | 0ac3c3429f443cd7d0f708a8b33706a1996d43fc /src/soc/intel/baytrail/romstage/romstage.c | |
parent | 8ba7023cf87413256bfc9c0902d9e69300e91a0b (diff) | |
download | coreboot-73c11194b0ea6a4fb93456fdff36cbd91838d4ec.tar.xz |
soc/amd: Implement common reset API
Add an `amdblocks` internal API and rename
soft_reset() => warm_reset()
hard_reset() => cold_reset()
as these terms are commonly used in the surrounding code.
On Stoney Ridge, make board_reset() call cold_reset() to keep
current behaviour of common code calling hard_reset(). But add
a TODO if this is intended.
Note: Stoney Ridge is using CF9 for the actual reset but the
configuration for a cold reset doesn't use the usual full reset
bit but some other mechanism.
Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/romstage.c')
0 files changed, 0 insertions, 0 deletions