diff options
author | Aaron Durbin <adurbin@chromium.org> | 2013-10-21 22:32:00 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@google.com> | 2014-02-16 20:57:14 +0100 |
commit | 7837be6cbb9dfacf66d0981e281c3d9a0a35767d (patch) | |
tree | aff1b53a14f8736a77e2ce29e78b4a07a19c4640 /src/soc/intel/baytrail/romstage/romstage.c | |
parent | 6a360048a1a4f8eaebbf9c4ec75fe4a9543421b2 (diff) | |
download | coreboot-7837be6cbb9dfacf66d0981e281c3d9a0a35767d.tar.xz |
baytrail: SMM support
Initialize SMM on all CPUs by relocating the SMM region
and setting SMRR on all the cores. Additionally SMI
is enabled in the south cluster.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi. Tested with DEBUG_SMI and noted
power button turns off board while in firmware.
Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173983
Reviewed-on: http://review.coreboot.org/4892
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/romstage.c')
-rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 3ab726df91..0149f1f351 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -34,6 +34,7 @@ #include <baytrail/pci_devs.h> #include <baytrail/reset.h> #include <baytrail/romstage.h> +#include <baytrail/smm.h> static inline uint64_t timestamp_get(void) { @@ -277,13 +278,13 @@ struct ramstage_cache *ramstage_cache_location(long *size) { char *smm_base; /* 1MiB cache size */ - const long cache_size = (1 << 20); + const long cache_size = CONFIG_SMM_RESERVED_SIZE; /* Ramstage cache lives in TSEG region which is the definition of * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; + return (void *)&smm_base[smm_region_size() - cache_size]; } void ramstage_cache_invalid(struct ramstage_cache *cache) |