diff options
author | Julius Werner <jwerner@chromium.org> | 2014-10-07 16:42:17 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-07 18:23:21 +0200 |
commit | 18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754 (patch) | |
tree | 875739d499ccc1fa84b03507f8bee699fb86eb95 /src/soc/intel/baytrail/romstage | |
parent | 26de1126363218cd19524050d80acc8ed1ce3e53 (diff) | |
download | coreboot-18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754.tar.xz |
baytrail: Change all SoC headers to <soc/headername.h> system
This patch aligns baytrail to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Rambi.
Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/romstage')
-rw-r--r-- | src/soc/intel/baytrail/romstage/early_spi.c | 6 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/gfx.c | 6 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/pmc.c | 12 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/raminit.c | 12 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 18 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/uart.c | 10 |
6 files changed, 32 insertions, 32 deletions
diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c index 6188f075fc..2c48af1698 100644 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ b/src/soc/intel/baytrail/romstage/early_spi.c @@ -22,9 +22,9 @@ #include <delay.h> #include <console/console.h> -#include <baytrail/iomap.h> -#include <baytrail/romstage.h> -#include <baytrail/spi.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/spi.h> #define SPI_CYCLE_DELAY 10 /* 10us */ #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c index 592d1feaf8..f9bb9c9e8f 100644 --- a/src/soc/intel/baytrail/romstage/gfx.c +++ b/src/soc/intel/baytrail/romstage/gfx.c @@ -18,9 +18,9 @@ */ #include <arch/io.h> -#include <baytrail/gfx.h> -#include <baytrail/pci_devs.h> -#include <baytrail/romstage.h> +#include <soc/gfx.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> void gfx_init(void) { diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index c58a42c37e..b41359b7ff 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -22,12 +22,12 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_def.h> -#include <baytrail/iomap.h> -#include <baytrail/iosf.h> -#include <baytrail/lpc.h> -#include <baytrail/pci_devs.h> -#include <baytrail/pmc.h> -#include <baytrail/romstage.h> +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/romstage.h> #include "../chip.h" void tco_disable(void) diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 6f3b21e3c6..fbd38df13d 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -25,13 +25,13 @@ #include <console/console.h> #include <device/pci_def.h> #include <halt.h> -#include <baytrail/gpio.h> +#include <soc/gpio.h> #include <soc/intel/common/mrc_cache.h> -#include <baytrail/iomap.h> -#include <baytrail/iosf.h> -#include <baytrail/pci_devs.h> -#include <baytrail/reset.h> -#include <baytrail/romstage.h> +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/reset.h> +#include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 91548e3edf..029fee61ee 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -34,15 +34,15 @@ #include <romstage_handoff.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <baytrail/gpio.h> -#include <baytrail/iomap.h> -#include <baytrail/lpc.h> -#include <baytrail/pci_devs.h> -#include <baytrail/pmc.h> -#include <baytrail/reset.h> -#include <baytrail/romstage.h> -#include <baytrail/smm.h> -#include <baytrail/spi.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/reset.h> +#include <soc/romstage.h> +#include <soc/smm.h> +#include <soc/spi.h> /* The cache-as-ram assembly file calls romstage_main() after setting up * cache-as-ram. romstage_main() will then call the mainboards's diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c index e46237ac1d..7705746b9e 100644 --- a/src/soc/intel/baytrail/romstage/uart.c +++ b/src/soc/intel/baytrail/romstage/uart.c @@ -18,11 +18,11 @@ */ #include <arch/io.h> -#include <baytrail/gpio.h> -#include <baytrail/iomap.h> -#include <baytrail/lpc.h> -#include <baytrail/pci_devs.h> -#include <baytrail/romstage.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> void byt_config_com1_and_enable(void) { |