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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-11-29 14:16:49 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-05 13:33:32 +0000 |
commit | d5d20d03fea5d50152fac783cb0985dbaa66d782 (patch) | |
tree | 0b020ad67d2a82f5371321d402b54631203e1990 /src/soc/intel/baytrail/romstage | |
parent | f6cfbf380488d74f5b420d90d02e59399b83fed9 (diff) | |
download | coreboot-d5d20d03fea5d50152fac783cb0985dbaa66d782.tar.xz |
soc/intel/baytrail: Implement POSTCAR stage
Use common code to tear down CAR.
Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/romstage')
-rw-r--r-- | src/soc/intel/baytrail/romstage/cache_as_ram.inc | 88 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 11 |
2 files changed, 9 insertions, 90 deletions
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index a3a062c19c..945b56d160 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -197,95 +197,11 @@ before_romstage: post_code(0x2a) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %ebx - post_code(0x2b) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x2c) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - invd - - post_code(0x2d) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x2e) - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x2f) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x30) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x31) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) .Lhlt: - post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index dd1fd29c7d..0e1d57e3dd 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -47,7 +47,7 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void *setup_stack_and_mtrrs(void); +static void platform_enter_postcar(void); static void program_base_addresses(void) { @@ -128,7 +128,10 @@ void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, /* Call into mainboard. */ mainboard_romstage_entry(&rp); - return setup_stack_and_mtrrs(); + platform_enter_postcar(); + + /* We don't return here */ + return NULL; } static struct chipset_power_state power_state CAR_GLOBAL; @@ -245,7 +248,7 @@ static inline uint32_t *stack_push(u32 *stack, u32 value) /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_stack_and_mtrrs(void) +static void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -267,5 +270,5 @@ static void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); } |