summaryrefslogtreecommitdiff
path: root/src/soc/intel/baytrail/smm.c
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-06 12:07:05 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-08 07:51:18 +0000
commit056fbe49ff9cccc7646371452431a05b47544057 (patch)
tree4bc2ea46dae5de31731678ba2eb86fa698034a3c /src/soc/intel/baytrail/smm.c
parentc86fc8e63d81251a5da80ed55e4fbc9900a900d9 (diff)
downloadcoreboot-056fbe49ff9cccc7646371452431a05b47544057.tar.xz
ELOG, soc/intel: Avoid some preprocessor use
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/smm.c')
-rw-r--r--src/soc/intel/baytrail/smm.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 4f019229e4..9f10f70b61 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -38,7 +38,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
- southcluster_log_state();
+ if (CONFIG(ELOG))
+ southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());