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authorFrans Hendriks <fhendriks@eltan.com>2018-10-29 14:17:16 +0100
committerFelix Held <felix-coreboot@felixheld.de>2018-11-23 17:16:18 +0000
commit802f43d67fc12c738325c860c5547e33141cff66 (patch)
tree1599063a86ef92fb5e1c2b677ce76feb120e667a /src/soc/intel/baytrail/southcluster.c
parent2f1ef98bdcea248671bf2b5ad1547c1dcfec2c64 (diff)
downloadcoreboot-802f43d67fc12c738325c860c5547e33141cff66.tar.xz
src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines
The GPIO and ACPI base sizes have defines, but they are not used. Use GPIO_BASE_SIZE and ACPI_BASE_SIZE. BUG=N/A TEST=Intel BayTrail CRB Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Huang Jin <huang.jin@intel.com>
Diffstat (limited to 'src/soc/intel/baytrail/southcluster.c')
-rw-r--r--src/soc/intel/baytrail/southcluster.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index c8e08dd8f0..d5e3400e6f 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -106,10 +107,10 @@ static void sc_add_io_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIO */
- sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE);
+ sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE);
/* ACPI */
- sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
+ sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
}
static void sc_read_resources(struct device *dev)