rambi/baytrail: ACPI, GPIO, audio, misc updates

rambi: Change RAM_ID GPIOs to GPIO_INPUT
Reviewed-on: https://chromium-review.googlesource.com/182934
(cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0)

baytrail: initialize rtc device
Reviewed-on: https://chromium-review.googlesource.com/183051
(cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821)

baytrail: Set SOC power budget values for SdpProfile 2&3
Reviewed-on: https://chromium-review.googlesource.com/183101
(cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55)

baytrail: Set PMC PTPS register correctly
Reviewed-on: https://chromium-review.googlesource.com/183280
(cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad)

baytrail: update to version 809 microcode for c0
Reviewed-on: https://chromium-review.googlesource.com/183256
(cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e)

baytrail: Add a shared GNVS init function
Reviewed-on: https://chromium-review.googlesource.com/183332
(cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c)

baytrail: Add basic support for ACPI System Wake Source
Reviewed-on: https://chromium-review.googlesource.com/183333
(cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619)

baytrail: allow configuration of io hole size
Reviewed-on: https://chromium-review.googlesource.com/183269
(cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919)

baytrail: add in C0 stepping idenitification support.
Reviewed-on: https://chromium-review.googlesource.com/183594
(cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4)

baytrail: add option for enabling PS2 mode
Reviewed-on: https://chromium-review.googlesource.com/183595
(cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f)

rambi: enable PS2 mode for VNN and VCC
Reviewed-on: https://chromium-review.googlesource.com/183596
(cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9)

baytrail: add config option for disabling slp_x stretching
Reviewed-on: https://chromium-review.googlesource.com/183587
(cherry picked from commit f99804c2649bef436644dd300be2a595659ceece)

rambi: disable slp_x stretching after sus fail
Reviewed-on: https://chromium-review.googlesource.com/183588
(cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880)

baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI
Reviewed-on: https://chromium-review.googlesource.com/183597
(cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906)

rambi: fix trackpad and touchscreen wake sources
Reviewed-on: https://chromium-review.googlesource.com/183598
(cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5)

baytrail: Add support for LPE device in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184006
(cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f)

rambi: Add LPE GPIOs for Jack/Mic detect
Reviewed-on: https://chromium-review.googlesource.com/184007
(cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578)

rambi: Set TSRx passive threshold to 60C
Reviewed-on: https://chromium-review.googlesource.com/184008
(cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee)

baytrail: DPTF: Add PPCC object for power limit information
Reviewed-on: https://chromium-review.googlesource.com/184158
(cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b)

baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant
Reviewed-on: https://chromium-review.googlesource.com/184442
(cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd)

rambi: Move the CPU passive/critical threshold config to DPTF
Reviewed-on: https://chromium-review.googlesource.com/184443
(cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac)

baytrail: Fix XHCI controller reset on resume
Reviewed-on: https://chromium-review.googlesource.com/184500
(cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd)

baytrail: update lpe audio firmware location
Reviewed-on: https://chromium-review.googlesource.com/184481
(cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6)

rambi: Put LPSS devices in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184530
(cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1)

baytrail: initialize HDA device and HDMI codec
Reviewed-on: https://chromium-review.googlesource.com/184710
(cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961)

baytrail: provide GPIO_ACPI_WAKE configuration
Reviewed-on: https://chromium-review.googlesource.com/184718
(cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b)

rambi: configure wake pins as just wake sources
Reviewed-on: https://chromium-review.googlesource.com/184719
(cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115)

baytrail: I2C: Add config data to ACPI Device
Reviewed-on: https://chromium-review.googlesource.com/184922
(cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8)

Squashed 28 commits for rambi and baytrail.

Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 33 insertions, 9 deletions

diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index e3facb997b..8d076c2fa2 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <arch/acpi.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -86,10 +87,6 @@ const struct reg_script xhci_init_script[] = {
 	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000),
 	/* BAR + 0x8060[25]=1b */
 	REG_RES_OR32(PCI_BASE_ADDRESS_0,  0x8060, 0x02000000),
-	/* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */
-	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040),
-	/* BAR + 0x80e0 toggle bit 24=0 */
-	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0),
 	/* BAR + 0x80f0[20]=0b */
 	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0),
 	/* BAR + 0x8008[19]=1b (to enable LPM) */
@@ -110,6 +107,28 @@ const struct reg_script xhci_init_script[] = {
 	REG_SCRIPT_END
 };
 
+const struct reg_script xhci_init_boot_script[] = {
+	/* Setup USB3 phy */
+	REG_SCRIPT_NEXT(usb3_phy_script),
+	/* Initialize host controller */
+	REG_SCRIPT_NEXT(xhci_init_script),
+	/* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */
+	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040),
+	/* BAR + 0x80e0 toggle bit 24=0 */
+	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0),
+	REG_SCRIPT_END
+};
+
+const struct reg_script xhci_init_resume_script[] = {
+	/* Setup USB3 phy */
+	REG_SCRIPT_NEXT(usb3_phy_script),
+	/* Initialize host controller */
+	REG_SCRIPT_NEXT(xhci_init_script),
+	/* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */
+	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040),
+	REG_SCRIPT_END
+};
+
 const struct reg_script xhci_clock_gating_script[] = {
 	/* ConfigureXhciClockGating() */
 	/* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */
@@ -165,6 +184,9 @@ static void xhci_route_all(device_t dev)
 	/* Route ports to XHCI controller */
 	reg_script_run_on_dev(dev, xhci_route_all_script);
 
+	if (acpi_slp_type == 3)
+		return;
+
 	/* Reset enabled USB3 ports */
 	port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
 	for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) {
@@ -178,10 +200,6 @@ static void xhci_init(device_t dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
 	struct reg_script xhci_hc_init[] = {
-		/* Setup USB3 phy */
-		REG_SCRIPT_NEXT(usb3_phy_script),
-		/* Initialize host controller */
-		REG_SCRIPT_NEXT(xhci_init_script),
 		/* Initialize clock gating */
 		REG_SCRIPT_NEXT(xhci_clock_gating_script),
 		/* Finalize XHCC1 and XHCC2 */
@@ -203,7 +221,13 @@ static void xhci_init(device_t dev)
 		REG_SCRIPT_END
 	};
 
-	/* Initialize XHCI controller */
+	/* Initialize XHCI controller for boot or resume path */
+	if (acpi_slp_type == 3)
+		reg_script_run_on_dev(dev, xhci_init_resume_script);
+	else
+		reg_script_run_on_dev(dev, xhci_init_boot_script);
+
+	/* Finalize Initialization */
 	reg_script_run_on_dev(dev, xhci_hc_init);
 
 	/* Route all ports to XHCI if requested */